1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device including a circuit for supplying an internal power supply voltage to internal circuitry.
2. Description of the Background Art
Referring to FIG. 25, a semiconductor memory device 2600 includes a memory cell array 105 including a plurality of memory cells arranged in rows and columns, a plurality of word lines WL and bit lines BL connected to the plurality of memory cells, a row decoder 107 for selecting a word line in response to a row address, a sense amplifier 109 for amplifying data read from a memory cell to the bit line BL, an input initial stage 120 for converting an external signal to an internal signal, an address buffer 106 for converting an external address (hereinafter referred to as ext.Add) to an internal address, a column system 130 which operates in response to a column address, a boosted voltage generating circuit (hereinafter referred to as Vpp circuit) 118 for generating a boosted voltage Vpp, a voltage lowering circuit for sense amplifier supplying an internal power supply voltage to sense amplifier 109 (hereinafter referred to as a sense amplifier VDC (voltage down converter) circuit) 116, and a voltage lowering circuit for peripherals (hereinafter referred to as VDC circuit for peripherals) 2601 for supplying an internal power supply voltage to periphery circuits other than output buffer 122 in column system 130, sense amplifier 109 and input initial stage 120.
Input initial stage 120 includes an RAS buffer 101 for converting an external word address strobe signal (hereinafter referred to as an ext./RAS) to an internal row address strobe signal (hereinafter referred to as an int./RAS), a CAS buffer 102 for converting an external column address strobe signal (hereinafter referred to as an ext./CAS) to an internal column address strobe signal (hereinafter referred to as an int./CAS), a WE buffer 103 for converting an external write enable signal (hereinafter referred to an ext./WE) to an internal write enable signal (hereinafter referred to as an int./WE), and an output enable buffer (hereinafter referred to as an OE buffer) 104 for converting an external output enable signal (hereinafter referred to as an ext./OE) to an internal output enable signal (hereinafter referred to as an int./OE).
Column system 130 includes a column decoder 108 for selecting a bit line in response to a column address, a preamplifier 111 for amplifying data read from a memory cell connected to the selected bit line, an output buffer 112 for supplying output data to an external data input/output pin (hereinafter referred to as an ext.DQ pin), a clock generating circuit 113 for generating a clock signal for controlling preamplifier 111 and output buffer 112, a data input buffer 114 receiving input data from ext.DQ pin, and a write driver 115 for writing input data to the memory cell.
Referring to FIG. 26, the VDC circuit 2601 for peripherals includes an output node N1 for outputting an internal power supply voltage (hereinafter referred to as int.Vcc), a driver transistor 201 formed of a p channel MOS transistor (hereinafter referred to as a PMOS transistor), and a differential amplifier 205.
Driver transistor 201 has its source electrode connected to a power supply node to which an external power supply voltage (hereinafter referred to as ext.Vcc) is applied, its drain electrode connected to a non-inverted input terminal (+) of differential amplifier 205 as well as to output node N1, and its gate electrode connected to an output terminal of differential amplifier 205. To the inverted terminal (-) of differential amplifier 205, a reference voltage Vref is applied.
In VDC circuit 2601 for peripherals, the voltage int. Vcc at output node N1 is compared with reference voltage Vref, and gate voltage of PMOS transistor 205 is controlled such that int.Vcc becomes equal to the reference voltage Vref. As a result, int.Vcc is generated based on ext.Vcc, and supplied to the peripheral circuits of the semiconductor memory device 2600.
In semiconductor memory device 2600, ext./RAS and ext./CAS are converted to int./RAS and int./CAS by RAS buffer 101 and CAS buffer 102, respectively. Here, when ext.Add is input and taken in the address buffer 106, row and column addresses are generated. A memory cell connected to the word line and bit line corresponding to the row and column addresses is selected, and data is read from or written to the selected memory cell.
At the time of data reading, a word line corresponding to the row address is selected by row decoder 107, and data is read to a plurality of bit lines from a plurality of memory cells connected to the selected word line, and the data is amplified by sense amplifier 109. In response to a column address, a bit line is selected, and the amplified data is transmitted from the selected bit line through an input/output line (hereinafter referred to as an I/O line) 110 through preamplifier 11. Data is further amplified by preamplifier 11 and output to ext.DQ pin through output buffer 112. Timing of output from preamplifier 111 and output buffer 112 as well as the timing of equalization are controlled by the clock signal from clock generating circuit 113.
At the time of data writing, data input through ext.DQ pin is transmitted to write driver 115 through data in buffer 114. Similar to the reading operation, a word line corresponding to the row address is selected by row decoder 107, and thereafter a bit line corresponding to the column address is selected by column decoder 108. The data from write driver 115 is applied to the selected bit line through I/O line 110, and written to the memory cell connected to the word line and a bit line.
Therefore, in one cycle of reading/writing operation, the power consumption of the semiconductor memory device increases only when the peripheral circuitry, mainly the column system 130 operating in response to the column address, is in operation.
However, when the gain of the VDC circuit 2601 for peripherals is increased to improve supplying capability of int.Vcc of the VDC circuit 2601 for peripherals provided in the conventional semiconductor memory device 2600 shown in FIG. 25, there is a possibility of oscillation if the gain is too large, as the VDC circuit 2601 for peripherals shown in FIG. 26 has the voltage at output node N1 fed back.
Referring to FIG. 27, another conventional semiconductor memory device 2800 includes, in stead of preamplifier 111, output buffer 112, data in buffer 114 and write driver 115 of the semiconductor memory device 2600 of FIG. 25, preamplifiers 111a and 111b, output buffers 112a and 112b, data in buffers 114a and 114b, as well as write drivers 115a and 115b.
In this device, input/output circuits 1, 2 having a plurality of ext.DQ pins are provided, and between the input/output circuits 1, 2 and VDC circuit 2601 for peripherals, a pad 1705 which is selectively connected to ext.Vcc or to the GND is further provided.
Other circuit configuration and operation are the same as the semiconductor memory device 2600. Therefore, description thereof is not repeated.
The semiconductor memory device 2800 allows selection of any of a plurality of word configurations, for example, .times.1, .times.4, .times.8, and .times.16 words configurations. When the .times.4 word configuration is selected, four bits of data are simultaneously input/output in response to an applied one address. The word configuration is selected by an activating signal generated based on the voltage on pad 1705.
In the semiconductor memory device which allows selection of word configurations, the larger the number of data to be input/output, the larger the peripheral circuitry. Therefore, when a larger word configuration is selected, power consumption increases. Therefore, as in the column system operation described above, when the supplying capability of VDC 2601 for peripherals is to be increased, there is higher possibility of oscillation of VDC circuit 2601 for peripherals.